1. Field of the Invention
This invention relates to circuit design verification systems, and, in particular, to a method and apparatus for verifying that the design of electronic circuits meets user specified operational correctness and performance criteria.
2. Description of the Related Art
Increases in precision, accuracy, and sophistication of fabrication techniques permit the design and manufacture of incredibly complex, large scale integrated circuits (xe2x80x9cICsxe2x80x9d). Not surprisingly, the resulting complexity and scale is reflected in the design effort for such ICs. The design effort typically involves many circuit designers and many iterations before a final design is ready for production. Various designs are proposed, tested, and modified. Each design is tested for bugs and for performance (i e., speed), and modified accordingly to remove bugs and/or improve performance. Ultimately, a design is deemed sufficiently bug-free and fast to be frozen and converted to hardware. Thus, one reason for the many iterations is to arrive at a design as good and complete as is reasonably possible.
One part of the design process is to xe2x80x9cverify,xe2x80x9d ie., test, that the design works acceptably. Verifying the correctness of complex ICs can be a difficult and complicated task. Various software representations of the IC design are employed during development. Typically, a logical representation of the IC is provided in a hardware design language (xe2x80x9cHDLxe2x80x9d) such as Verilog or VHDL. This representation is, in fact, a computer based modelxe2x80x94an inchoate description of the IC hardware for a design proposed in a particular iteration. Ultimately, when the IC design is frozen, the HDL representation is converted to an arrangement of gates capable of implementing the IC logic on a semiconductor chip.
More particularly, the IC is represented by a list of statements in an HDL. This list of statements is referred to as the HDL circuit xe2x80x9cspecificationxe2x80x9d or xe2x80x9cdescription.xe2x80x9d The HDL circuit description is then converted into a specific circuit xe2x80x9cnetlist.xe2x80x9d The netlist comprises a list of circuit components and the interconnections between those components. Circuit components are also known as xe2x80x9ccells,xe2x80x9d where each cell in a specific circuit library has both a logical representation, as well as a circuit layout representation.
The netlist defines all of the interconnections between the components of the circuit. Each xe2x80x9csignalxe2x80x9d which interconnects two or more cells, or which represents an input or output for the entire circuit, is actually a node in the circuit which has been assigned a name. Many circuits receive input signals on more than one input terminal, and produce output signals only after multiple required input signal changes have occurred on multiple input terminals. Usually, the time at which the output signal occurs depends not only upon the arrival time of the latest required input signal, but also upon the prior arrival times of other required input signals. In conventional circuit analysis and design, simple models are used that represent circuit operation as providing the output signal after a fixed delay following the arrival of the last required input signal. The terms xe2x80x9cnet,xe2x80x9d xe2x80x9csignalxe2x80x9d and xe2x80x9cnodexe2x80x9d are sometimes used interchangeably. In addition, the netlist specifies the nature of its components by specifying a cell name for each component. The cell name, in turn, specifies or points to a particular circuit in a predefined library of cells.
In fact, complex custom ICs are often designed by engineers at the xe2x80x9cHDL levelxe2x80x9d and are specified by those engineers for simulation and verification purposes using an HDL circuit description such as a Verilog language circuit description. To create the conditions used to detect defects in a circuit design, highly parallel but well-controlled verification programs are written. In such programs, test patterns are applied to the input ports in the HDL circuit description and signals at the output ports are observed over time to determine whether the inputs were transformed into the expected outputs. The HDL circuit description is sometimes referred to as the xe2x80x9cdevice under testxe2x80x9d (xe2x80x9cDUTxe2x80x9d). Thus, the DUT is xe2x80x9csurroundedxe2x80x9d with a layer of code that performs the stimulus generation and output comparisons. This layer of code, often referred to as a xe2x80x9ctest bench,xe2x80x9d can be very simple or as complex as necessary for the application at hand.
In current approaches, one difficulty in creating complex test benches arises when there are many types of events that are not expected to happen at specific times, but rather xe2x80x9csome timexe2x80x9d within a certain relationship to other events. For example, in a bus transaction, a designer might send a request and want to have it acknowledged within a certain window of time. However, whether the reply comes within 2 or 20 cycles might be irrelevant. Similarly, an arbiter may assign a given resource in ways that are difficult to predict and may not matter. What will actually matter is that in the end all the requests presented to the arbiter for servicing are satisfied by the arbiter and that the ordering satisfies a specified general policy.
These two examples reflect a common problem in the verification of complex circuits, namely that the inherently parallel nature of complex electronic circuits results in time and ordering ambiguities or uncertainties. The circuit simulator on which the HDL circuit netlist description is being verified traces the various signals that propagate through the model when the test bench is performed. The circuit simulator will generate a xe2x80x9c1xe2x80x9d (logic high), xe2x80x9c0xe2x80x9d (logic low), xe2x80x9cZxe2x80x9d (tristate), or xe2x80x9cXxe2x80x9d (unknown) value for a given signal at a given time. The xe2x80x9cXxe2x80x9d values arise from these ordering ambiguities and uncertainties. For instance, an xe2x80x9cXxe2x80x9d value may be caused by failure to meet timing constraints (e.g., set-up and hold times), or by the receipt of an xe2x80x9cXxe2x80x9d input signal. The xe2x80x9cXxe2x80x9d value then propagates downstream to other cells, generating still more xe2x80x9cXxe2x80x9d values in a xe2x80x9clogic conexe2x80x9d extending from the first cell, until they appear at the primary outputs of the circuit simulator.
These unknowns are a serious problem to the circuit designers because an unknown implies that the resulting output is unpredictable. Circuit designers, therefore, have to explain the source of each unknown so that it can be fixed in the next design iteration. Circuit designers typically use debugging tools of simulation waveform dumps (of the signals) to find the source of these unknowns. This frequently involves tracing back through the model to examine the internal states of the nodes of the circuits during the test bench. The unknowns are traced back to the driven cells and all the nodes in the entire logic cone have to be examined to find the origin, or source, of the first unknown.
Thus, state of the art tools available for isolating the root of these unknown values do not offer any quick or convenient ways to accomplish this identification. In a sense, the state of the art still employs a brute force approachxe2x80x94checking all signal drivers and their logic values throughout the entire logic cone. This is especially difficult since the logic cone is defined by the root, which is still unknown at the time. This can be a tedious and time consuming task for state of the art IC design netlists where the number of logic levels leading to the root of a logic cone is very high.
In its various aspects and embodiments, the invention includes a method and apparatus for simulating and verifying an integrated circuit design.
In first aspect, the invention includes a circuit simulation system for use in verifying a design of an integrated circuit. The circuit simulator comprises a test bench, an HDL circuit specification of the integrated circuit design, at least one circuit model for use in implementing the HDL circuit specification, and a circuit simulator. The circuit simulator includes a simulation engine and at least one data structure. The simulation engine is capable of simulating the integrated circuit design from the HDL circuit specification in accordance with the test bench. The data structure is for use in simulating the integrated circuit design and includes a root unknown value and a unique identifier for a root cell generating the root unknown value.
In a second aspect, the invention includes a method for isolating the root of unknown values in an HDL simulation. The method comprises simulating the operation of an integrated circuit; tracking a plurality of values of a plurality of signals during the simulation; and marking a root unknown value with a unique identifier for a root cell generating the root unknown value as the root unknown value is tracked.
In other aspects, the invention includes a program storage medium encoded with instructions and/or a computing device programmed with such instruction to perform the method, either by using such a simulation circuit or some other simulation circuit.